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| rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9709 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 8-bit, 125 msps dual txdac+ d/a converter product description the AD9709 is a dual-port, high-speed, two-channel, 8-bit cmos dac. it integrates two high-quality 8-bit txdac+ cores, a voltage reference, and digital interface circuitry into a small 48-lead lqfp package. the AD9709 offers exceptional ac and dc performance while supporting update rates up to 125 msps. the AD9709 has been optimized for processing i and q data in communications applications. the digital interface consists of two double-buffered latches as well as control logic. separate write inputs allow data to be written to the two dac ports independent of one another. separate clocks control the update rate of the dacs. a mode control pin allows the AD9709 to interface to two sep- arate data ports, or to a single interleaved high-speed data port. in interleaving mode, the input data stream is demuxed into its original i and q data and then latched. the i and q data is then converted by the two dacs and updated at half the input data rate. the gainctrl pin allows two modes for setting the full-scale current (i outfs ) of the two dacs. i outfs for each dac can be set independently using two external resistors, or i outfs for both dacs can be set using a single external resistor. the dacs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and to maximize dynamic accuracy. each dac provides differential current output thus supporting single-ended or differential applications. both dacs can be simultaneously updated and provide a nominal full-scale current of 20 ma. the full-scale currents between each dac are matched to within 0.1%. the AD9709 is manufactured on an advanced low-cost cmos process. it operates from a single supply of 3.0 v to 5.0 v and consumes 380 mw of power. product highlights 1. the AD9709 is a member of a pin-compatible family of dual txdacs providing 8-, 10-, 12-, and 14-bit resolution. 2. dual 8-bit, 125 msps dacs: a pair of high-performance dacs optimized for low-distortion performance provide for flexible transmission of i and q information. 3. matching: gain matching is typically 0.1% of full-scale, and offset error is better than 0.02%. 4. low power: complete cmos dual dac function operates on 380 mw from a 3.0 v to 5.0 v single supply. the dac full-scale current can be reduced for lower power operation, and a sleep mode is provided for low-power idle periods. 5. on-chip voltage reference: the AD9709 includes a 1.20 v temperature-compensated bandgap voltage reference. 6. dual 8-bit inputs: the AD9709 features a flexible dual-port interface allowing dual or interleaved input data. features 8-bit dual transmit dac 125 msps update rate excellent sfdr to nyquist @ 5 mhz output = 66 dbc excellent gain and offset matching: 0.1% fully independent or single resistor gain control dual port or interleaved data on-chip 1.2 v reference single 5 v or 3 v supply operation power dissipation: 380 mw @ 5 v power-down mode: 50 mw @ 5 v 48-lead lqfp applications communications basestations digital synthesis quadrature modulation 3d ultrasound functional block diagram ? latch ? dac refio fsadj1 fsadj2 gainctrl reference bias generator i outa1 i outb1 sleep i outa2 i outb2 digital interface AD9709 port1 port2 wrt1 wrt2 dvdd dcom avdd acom clk1 clk2 mode ? dac ? latch txdac+ is a registered trademark of analog devices, inc. * patent pending.
#$# AD9709especifications dc specifications parameter min typ max unit resolution 8 bits dc accuracy 1 integral linearity error (inl) e0.5 ? ? ? #%# AD9709 dynamic specifications parameter min typ max unit dynamic performance maximum output update rate (f clock ) 125 msps output settling time (t st ) (to 0.1%) 1 35 ns output propagation delay (t pd )1ns glitch impulse 5 pv-s output rise time (10% to 90%) 1 2.5 ns output fall time (90% to 10%) 1 2.5 ns output noise (i outfs = 20 ma) 50 pa/ hz hz ? doubly terminated, unless otherwise noted) #&# AD9709especifications caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9709 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device digital specifications parameter min typ max unit digital inputs logic 1 voltage @ dvdd = 5 v 3.5 5 v logic 1 @ dvdd = 3 2.1 3 v logic 0 voltage @ dvdd = 5 v 0 1.3 v logic 0 @ dvdd = 3 0 0.9 v logic 1 current e10 +10 data in (wrt2) (wrt1 / iqwrt) (clk2) (clk1/ iqclk) iouta or ioutb t lpw t pd t s t h t cpw ' ( ) * (t min to t max , avdd = 5 v, dvdd = 5 v, i outfs = 20 ma, unless otherwise noted) ordering guide temperature package package model range description option AD9709ast e40 AD9709 #+# pin function descriptions pin no. name description 1e8 port1 data bits db7ep1 to db0ep1 9e14, 31e36 nc no connection 15, 21 dcom1, dcom2 digital common 16, 22 dvdd1, dvdd2 digital supply voltage 17 wrt1/iqwrt input write signal for port 1 (iqwrt in interleaving mode) 18 clk1/iqclk clock input for dac1 (iqclk in interleaving mode) 19 clk2/iqreset clock input for dac2 (iqreset in interleaving mode) 20 wrt2/iqsel input write signal for port 2 (iqsel in interleaving mode) 23e30 port2 data bits db7ep2 to db0ep2 37 sleep power-down control input 38 acom analog common 39, 40 i outa2 , i outb2 port 2 differential dac current outputs 41 fsadj2 full-scale current output adjust for dac2 42 gainctrl master/slave resistor control mode 43 refio reference input/output 44 fsadj1 full-scale current output adjust for dac1 45, 46 i outb1 , i outa1 port 1 differential dac current outputs 47 avdd analog supply voltage 48 mode mode select (1 = dual port, 0 = interleaved) pin configuration nc nc nc nc db0-p1 db1-p1 db2-p1 db3-p1 db4-p1 db5-p1 db6-p1 db7-p1(msb) nc nc nc nc nc nc db1-p2 db2-p2 db3-p2 db4-p2 db5-p2 db0-p2 AD9709 dual 8-bit dac 48-pin lqfp 12 11 10 9 8 7 6 5 4 3 2 1 26 27 28 29 30 31 32 33 34 35 36 25 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 pin 1 identifier mode avdd i outa1 i outb1 fsadj1 refio gain ctrl fsadj2 i outb2 i outa2 acom sleep nc nc dcom1 dvdd1 wrt1/iqwrt clk1/iqclk clk2/iqreset wrt/iqsel dcom2 dvdd2 db7-p2 (msb) db6-p2 nc = no connect AD9709 #,# definitions of specifications linearity error (also called integral nonlinearity or inl) linearity error is detned as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full-scale. differential nonlinearity (or dnl) dnl is the measure of the variation in analog value, normalized to full-scale, associated with a 1 lsb change in digital input code. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called offset error. for i outa , 0 ma output is expected when the inputs are all 0s. for i outb , 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. avdd digital data db0-db7 gainctrl 50 dvdd dcom retimed clock output lecroy 9210 pulse generator tektronix awg-2021 w/option 4 wrt1/ iqwrt 1.2v ref r set 2 2k channel 1 latch channel 2 latch pmos current source array pmos current source array segmented switches for dac1 segmented switches for dac2 lsb switch lsb switch multiplexing logic AD9709 dcom acom mode i outa1 i outb1 sleep clk2/ iqreset clk1/ iqclk 5v fsadj1 r set 1 2k refio 0.1 f fsadj2 db0-db7 wrt2/ iqsel 50 5v mini circuits t1-1t to hp3589a spectrum/ network analyzer *awg2021 clock retimed such that digital data transitions on falling edge of 50% duty cycle clock dvdd dac2 latch dac1 latch clk divider 50 i outa2 i outb2 ' $ - .. / )0 121 )3 ( 3 * 4 5!.)6 '07( '07$ temperature drift temperature drift is specited as the maximum change from the ambient (25 AD9709 #2# typical characterization curves (avdd = 5 v, dvdd = 3.3 v, i outfs = 20 ma, 50 doubly terminated load, differential output, t a = 25 c, sfdr up to nyquist, unless otherwise noted) sfdr e dbc 75 70 60 65 45 1 10 100 f out e mhz 0.1 50 55 f clk = 5msps f clk = 65msps f clk = 125msps f clk = 25msps ' % 0' 84) 9-'0 e 12dbfs f out e mhz sfdr e dbc 45 05 25 10 15 20 70 65 60 55 50 30 35 0dbfs e 6dbfs 75 ' ,0' 84) 9,+*030 a out e dbfs sfdr e dbc 2 5msps /0.46mhz e 25 e 19 e 7 65 40 50 45 55 60 e 16 70 e 22 e 13 e 10 e 4 e 1 75 10msps/0.91mhz 25msps/2.27mhz 65msps/5.91mhz 125msps/11.37mhz ' 10:) 0' 84) 9 84) ; .68.< =(( sfdr e dbc 0 2.5 0.5 1 1.5 2 70 55 50 45 0 dbfs e 6 dbfs e 12 dbfs 75 f out e mhz 65 60 ' & 0' 84) 9+*030 f out e mhz sfdr e dbc 45 0 10 50 20 30 40 75 70 65 55 50 60 60 70 0dbfs e 6dbfs e 12dbfs ' 2 0' 84) 9($+*030 a out e dbfs sfdr e dbc 45 0 e 20 e 15 e 5 65 50 55 40 60 70 e 10 5msps/1.0mhz 75 e 25 10msps/2.0mhz 25msps/5.0mhz 65msps/13.0mhz 125msps/5.0mhz ' ( 0:) 0' 84) 9 84) ; .68.< =+ f out e mhz sfdr e dbc 0 212 4 6 8 10 65 60 55 45 50 0dbfs e 6dbfs e 12dbfs 70 75 ' + 0' 84) 9$+*030 f out e mhz sfdr e dbc 50 0 10 20 30 75 70 60 55 65 51525 i outfs = 5ma i outfs = 10ma i outfs = 20ma 45 35 ' > 0' 84) 84)'0 9,+*030 -'0 a out e dbfs sfdr e dbc 75 0 e 20 e 10 e 5 55 40 50 60 e 15 45 3.3/3.4mhz @25msps 8.8/9.8mhz @65msps e 25 65 70 0.965/1.035mhz @7msps 16.9/18.1mz @125msps ' (( :) 0' 84) 9 84) ; .68.< =2 AD9709 #># f clk e msps sinad e dbc 40 20 140 40 60 80 100 120 55 60 65 i outfs = 5ma 70 45 50 0 i outfs = 10ma i outfs = 20ma ' ($ 0! .68.< 84)'0 9 84) ;+* / -'0 temperature e c sfdr e dbc 70 65 e 30 e 10 70 50 60 55 50 30 10 45 90 e 50 75 f out = 10mhz f out = 25mhz f out = 40mhz f out = 60mhz ' (+ 0') 9 .6< ;($+*030 -'0 frequency e mhz amplitude e dbm 40 20 0 e 90 e 80 e 70 e 60 e 50 e 40 e 30 e 20 e 10 0 10 30 50 60 ' (> :) 0'9 .6< ;($+*030 code dnl e lsbs e 0.01 0 50 0.01 0 0.07 0.06 0.05 0.04 0.03 0.02 100 150 200 250 ' (& ) !6 amplitude e dbm frequency e mhz 40 20 0 e 100 e 90 e 80 e 70 e 60 e 50 e 40 e 30 e 20 e 10 0 10 30 60 50 ' (2 0:) 0'9 .6< ;($+*030 code inl e lsbs e 0.1 e 0.08 e 0.06 e 0.04 e 0.02 0 0.02 0.04 0.06 0 256 224 192 160 128 96 64 32 ' (% ) !6 temperature e c offset error e % fs 0.05 e 0.05 e 40 e 200 20406080 0.03 0.00 e 0.03 gain error offset error 1.0 e 1.0 5 0.5 0.0 e 0.5 gain error e % fs ' (, 5 8 ) 9 .6< ;($+*030 frequency e mhz amplitude e dbm 40 20 0 e 90 e 80 e 70 e 60 e 50 e 40 e 30 e 20 e 10 0 10 30 60 50 ' (1 ' :) 0'9 .6< ;($+*030 AD9709 #1# functional description figure 20 shows a simplited block diagram of the AD9709. the AD9709 consists of two dacs, each one with its own independent digital control logic and full-scale output current control. each dac contains a pmos current source array capable of providing up to 20 ma of full-scale current (i outfs ). the array is divided into 31 equal currents that make up the tve most signitcant bits (msbs). the three lower bits consist of seven equal current sources whose value is 1/8th of an msb current source. implementing the lower bits with current sources, instead of an r-2r ladder, enhances the dynamic performance for multitone or low-amplitude signals and helps maintain the dacs high-output impedance (i.e., >100 k ? . input or output depending on whether the internal or an external reference is used. to use the internal reference, simply decouple the refio pin to acom with a 0.1 digital data inputs i ref1 i ref2 avdd db0-db7 gainctrl wrt1/ iqwrt 1.2v ref r set 2 2k channel 1 latch channel 2 latch pmos current source array pmos current source array segmented switches for dac1 segmented switches for dac2 lsb switch lsb switch multiplexing logic AD9709 dcom mode sleep clk2/ iqreset clk1/ iqclk 5v fsadj1 r set 1 2k refio 0.1 f fsadj2 db0-db7 wrt2/ iqsel 5v dvdd dac2 latch dac1 latch clk divider acom i outa1 i outb1 r l 1a 50 v out 1a r l 1b 50 v out 1b r l 2a 50 v out 2a r l 2b 50 v out 2b i outa2 i outb2 v diff = v out a e v out b ' $ 0 ?- @ AD9709 #(# reference control amplifier both of the dacs in the AD9709 contain a control ampliter that is used to regulate the full-scale output current, i outfs . the control ampliter is contgured as a v-i converter as shown in figure 21, so that its current output, i ref , is determined by the ratio of the v refio and an external resistor, r set , as stated in equation 4. i ref is copied to the segmented current sources with the proper scale factor to set i outfs as stated in equation 3. +1.2v ref avdd gainctrl current source array refio fsadj 2k 0.1 f additional external load optional external reference buffer AD9709 reference section i ref acom ' $( . ? +1.2v ref avdd gainctrl current source array refio fsadj 2k AD9709 reference section i ref acom avdd external reference ' $$ a . ? the control ampliter allows a wide (10:1) adjustment span of i outfs from 2 ma to 20 ma by setting i ref between 62.5 i outa = ( dac code /256) i outfs (1) i outb = (255 ? dac code )/256 i outfs (2) where dac code = 0 to 255 (i.e., decimal representation). as mentioned previously, i outfs is a function of the reference current i ref , which is nominally set by a reference voltage, v refio and external resistor r set . it can be expressed as: i outfs = 32 i ref (3) where i ref = v refio / r set (4) the two current outputs will typically drive a resistive load directly or via a transformer. if dc coupling is required, i outa and i outb should be directly connected to matching resistive loads, r load , that are tied to analog common, acom. note, r load may represent the equivalent load resistance seen by i outa or i outb as would be the case in a doubly terminated 50 ? ? v outa = i outa r load (5) v outb = i outb r load (6) note the full-scale value of v outa and v outb should not exceed the speci?d output compliance range to maintain speci?d distortion and linearity performance. v diff = ( i outa ?i outb ) r load (7) substituting the values of i outa , i outb and i ref ; v diff can be expressed as: v diff = {(2 dac code ?255)/256} r load / r set ) v refio (8) these last two equations highlight some of the advantages of operating the AD9709 differentially. first, the differential operation will help cancel common-mode error sources associ- ated with i outa and i outb such as noise, distortion and dc offsets. second, the differential code dependent current and subsequent voltage, v diff , is twice the value of the single-ended voltage output (i.e., v outa or v outb ), thus providing twice the signal power to the load. note, the gain drift temperature performance for a single-ended (v outa and v outb ) or differential output (v diff ) of the AD9709 can be enhanced by selecting temperature tracking resistors for r load and r set due to their ratiometric relationship as shown in equation 8. analog outputs the complementary current outputs in each dac, i outa and i outb , may be con?ured for single-ended or differential opera- tion. i outa and i outb can be converted into complementary single-ended voltage outputs, v outa and v outb , via a load resistor, r load , as described in the dac transfer function section by equations 5 through 8. the differential voltage, v diff , existing between v outa and v outb can also be converted to a single-ended voltage via a transformer or differential ampli?r con?uration. the ac performance of the AD9709 is optimum and speci?d using a differential transformer coupled output in which the voltage swing at i outa and i outb is limited to AD9709 #((# performing a differential-to-single-ended conversion via a trans- former also provides the ability to deliver twice the reconstructed signal power to the load (i.e., assuming no source termination). since the output currents of i outa and i outb are complementary, they become additive when processed differentially. a prop- erly selected transformer will allow the AD9709 to provide the required power and voltage levels to different loads. the output impedance of i outa and i outb is determined by the equivalent parallel combination of the pmos switches associ- ated with the current sources and is typically 100 k ? wrt1/wrt2 clk1/clk2 data in iouta or ioutb t lpw t pd t s t h t cpw ' $% * ) timing specitcations for dual port mode are given in figures 23 and 24. d1 d2 d3 d4 d5 datain wrt1/wrt2 clk1/clk2 xx d1 d2 d3 d4 iouta or ioutb ' $& * ) interleaved mode timing when the mode pin is at logic 0, the AD9709 operates in inter- leaved mode. wrt1 now functions as iqwrt and clk1 functions as iqclk. wrt2 functions as iqsel and clk2 functions as iqreset. data enters the device on the rising edge of iqwrt. the logic level of iqsel will steer the data to either channel latch 1 (iqsel = 1) or to channel latch 2 (iqsel = 0). note: for proper operation, iqsel should only change state when iqwrt and iqclk are low. AD9709 #($# when iqreset is high, iqclk is disabled. when iqreset goes low, the following rising edge on iqclk will update both dac latches with the data present at their inputs. in the inter- leaved mode iqclk is divided by 2 internally. following this first rising edge, the dac latches will only be updated on every other rising edge of iqclk. in this way, iqreset can be used to synchronize the routing of the data to the dacs. as with the dual port mode, iqclk should occur before or simultaneously with iqwrt. iqsel iqwrt dac1 latch dac1 interleaved data in, port 1 deinterleaved data out iqclk iqreset dac2 latch dac2 2 port 1 input latch port 2 input latch ' $+ 6 0 * timing specitcations for interleaved mode are given in figures 26 and 27. data in iqwrt iqclk iouta or ioutb t lpw t pd t s t h t h * iqsel * applies to falling edge of iqclk /iqwrt and iqsel only ' $, * ) d1 d2 d3 d4 d5 interleaved data xx xx d1 d2 d3 d4 xx iqsel iqwrt iqreset dac output port 1 dac output port 2 iqclk ' $2 * ) the digital inputs are cmos-compatible with logic thresholds, v threshold , set to approximately half the digital positive supply (dvdd) or v threshold = dvdd/2 ( ? ? dvdd digital input ' $> b note that the clock input could also be driven via a sine wave, which is centered around the digital threshold (i.e., dvdd/2) and meets the min/max logic threshold. this will typically result in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. also, at higher sampling rates, the 20% tolerance of the digital logic threshold should be considered since it will affect the effective clock duty cycle and, subsequently, cut into the required data setup and hold times. AD9709 #(%# time of data change relative to rising clock edge e ns sinad e dbc 0 e 4 e 2 0 23 e 3 e 1 4 1 10 20 30 40 50 60 ' $1 0!. @3 9 84) ;$* / input clock and data timing relationship snr in a dac is dependent on the relationship between the position of the clock edges and the point in time at which the input data changes. the AD9709 is rising edge triggered, and so exhibits snr sensitivity when the data transition is close to this edge. in general, the goal when applying the AD9709 is to make the data transition close to the falling clock edge. this becomes more important as the sample rate increases. figure 29 shows the relationship of snr to clock/data placement. sleep mode operation the AD9709 has a power down function that turns off the output current and reduces the supply current to less than 8.5 ma over the specited supply range of 3.0 v to 5.5 v and temperature range. this mode can be activated by applying a logic level 1 to the sleep pin. the sleep pin logic threshold is equal to 0.5 i outfs e ma 0510 10 i avdd e ma 20 30 40 50 60 70 80 15 20 25 ' % 84)'0 ratio e f out /f clk 0 0.1 0 i dvdd e ma 5 10 15 20 25 30 35 0.2 0.3 0.4 0.5 125msps 100msps 65msps 25msps 5msps ' %( 9;+ ratio e f out /f clk 0 0.1 0 i dvdd e ma 2 4 6 8 10 12 14 0.2 0.3 0.4 0.5 16 18 125msps 100msps 65msps 25msps 5msps ' %$ 9;% AD9709 #(&# a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage will result if i outa and/or i outb is connected to an appropriately sized load resistor, r load , referred to acom. this contguration may be more suitable for a single-supply system requiring a dc- coupled, ground referred output voltage. alternatively, an ampliter could be contgured as an i-v converter, thus converting i outa or i outb into a negative unipolar voltage. this contguration provides the best dc linearity since i outa or i outb is maintained at a virtual ground. note that i outa provides slightly better perfor- mance than i outb . differential coupling using a transformer an rf transformer can be used to perform a differential-to- single-ended signal conversion as shown in figure 33. a differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer?s passband. an rf transformer such as the mini-circuits t1-1t provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load. transformers with different impedance ratios may also be used for impedance matching purposes. note that the transformer provides ac coupling only. r load AD9709 mini-circuits t1-1t optional r diff i outa i outb ' %% 8 4 ) the center tap on the primary side of the transformer must be connected to acom to provide the necessary dc current path for both i outa and i outb . the complementary voltages appearing at i outa and i outb (i.e., v outa and v outb ) swing symmetrically around acom and should be maintained with the specited output compliance range of the AD9709. a differential resistor, r diff , may be inserted in applications where the output of the transformer is connected to the load, r load , via a passive reconstruction tlter or cable. r diff is determined by the transformer?s impedance ratio and provides the proper source termination that results in a low vswr. note that approximately half the signal power will be dissipated across r diff . differential coupling using an op amp an op amp can also be used to perform a differential to single- ended conversion as shown in figure 34. the AD9709 is contgured with two equal load resistors, r load , of 25 ? ? ? AD9709 500 225 225 500 25 25 ad8047 c opt i outa i outb ' %& . . 4 8 AD9709 i outa i outb c opt 500 225 225 500 25 25 ad8041 1k avdd ' %+ 00 . . . AD9709 50 i outa i outb ' %, +4 8 AD9709 #(+# single-ended, buffered voltage output configuration figure 37 shows a buffered single-ended output contguration in which the op amp u1 performs an i-v conversion on the AD9709 output current. u1 maintains i outa (or i outb ) at a virtual ground, thus minimizing the nonlinear output imped- ance effect on the dac?s inl performance as discussed in the analog output section. although this single-ended contgu- ration typically provides the best dc linearity performance, its ac distortion performance at higher dac update rates may be limited by u1?s slewing capabilities. u1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of r fb and i outfs . the full-scale output should be set within u1?s voltage output swing capabilities by scaling i outfs and/or r fb . an improvement in ac distortion performance may result with a reduced i outfs since the signal current u1 will be required to sink will be subsequently reduced. i outa i outb AD9709 200 u1 v out = i outfs r fb r fb 200 ' %2 4 - 8 frequency e mhz psrr e db 90 70 0.2 85 80 75 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 ' %> 3 0 c power and grounding considerations, power supply rejection many applications seek high-speed and high-performance under less than ideal operating conditions. in these application circuits, the implementation and construction of the printed circuit board is as important as the circuit design. proper rf techniques must be used for device selection, placement and routing as well as power supply bypassing and grounding to ensure optimum performance. one factor that can measurably affect system performance is the ability of the dac output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. this is referred to as the power supply rejection ratio. for dc variations of the power supply, the resulting performance of the dac directly corresponds to a gain error associated with the dac?s full-scale current, i outfs . ac noise on the dc supplies is common in applications where the power distribution is gen- erated by a switching power supply. typically, switching power supply noise will occur over the spectrum from tens of khz to several mhz. the psrr vs. frequency of the AD9709 avdd supply over this frequency range is shown in figure 38. note that the units in figure 38 are given in units of (amps out/ volts in). noise on the analog power supply has the effect of modulating the internal current sources, and therefore the output cur rent. the voltage noise on avdd, therefore, will be added in a nonlinear manner to the desired i out . psrr is very code dependent, thus producing mixing effects which can modulate low- frequency power supply noise to higher frequen- cies. worst case psrr for either one of the differential dac outputs will occur when the full-scale current is directed to- wards that output. as a result, the psrr measurement in fig- ure 38 represents a worst-case condition in which the digital inputs remain static and the full-scale output current of 20 ma is directed to the dac output being measured. an example serves to illustrate the effect of supply noise on the analog supply. suppose a switching regulator with a switching frequency of 250 khz produces 10 mv of noise and for simplic- ity sake (i.e., ignore harmonics), all of this noise is concentrated at 250 khz. to calculate how much of this undesired noise will appear as current noise superimposed on the dc?s full-scale current, i outfs , one must determine the psrr in db using figure 38 at 250 khz. to calculate the psrr for a given r load , such that the units of psrr are converted from a/v to v/v, adjust the curve in figure 38 by the scaling factor 20 100 f 10 f e 22 f 0.1 f ttl/cmos logic circuits +5v power supply ferrite beads avdd acom electrolytic tantalum ceramic ' %1 6.' 0+ % for those applications that require a single 5 v or 3 v supply for both the analog and digital supplies, a clean analog supply may be generated using the circuit shown in figure 39. the circuit consists of a differential lc tlter with separate power supply and return lines. lower noise can be attained by using low-esr type electrolytic and tantalum capacitors. AD9709 #(,# applications using the AD9709 for quadrature amplitude modulation qam is one of the most widely used digital modulation schemes in digital communications systems. this modulation technique can be found in fdm as well as spread spectrum (i.e., cdma) based systems. a qam signal is a carrier frequency that is modulated in both amplitude (i.e., am modulation) and phase (i.e., pm modulation). it can be generated by independently modulating two carriers of identical frequency but with a 90 dac carrier frequency 8 8 to mixer nyquist filters quadrature modulator dac dsp or asic 0 90 ' & ) d* a common and traditional implementation of a qam modula- tor is shown in figure 40. the modulation is performed in the analog domain in which two dacs are used to generate the baseband i and q components. each component is then typically applied to a nyquist tlter before being applied to a quadrature mixer. the matching nyquist tlters shape and limit each com- ponents spectral envelope while minimizing intersymbol inter- ference. the dac is typically updated at the qam symbol rate or possibly a multiple of it if an interpolating tlter precedes the dac. the use of an interpolating tlter typically eases the implementation and complexity of the analog tlter, which can be a signitcant contributor to mismatches in gain and phase between the two baseband channels. a quadrature mixer modu- lates the i and q components with the in-phase and quadrature carrier frequency and then sums the two outputs to provide the qam signal. in this implementation, it is much more diftcult to maintain proper gain and phase matching between the i and q channels. the circuit implementation shown in figure 41 helps improve upon the matching between the i and q channels, as well as showing a path for up-conversion using the ad8346 quadrature modulator. the AD9709 provides both i and q dacs as well as a common reference that will improve the gain matching and stability. r cal can be used to compensate for any mismatch in gain between the two channels. the mismatch may be attributed to the mismatch between r set1 and r set2 , effective load resis- tance of each channel, and/or the voltage offset of the control ampliter in each dac. the differential voltage outputs of both dacs in the AD9709 are fed into the respective differential inputs of the ad8346 via matching networks. i and q digital data can be fed into the AD9709 in two different ways. in dual port mode, the digital i information drives one input port, while the digital q information drives the other input port. if no interpolation tlter precedes the dac, the symbol rate will be the rate at which the system clock drives the clk and wrt pins on the AD9709. in interleaved mode, the digital input stream at port i contains the i and the q information in alternating digital words. using iqsel and iqreset, the AD9709 can be synchronized to the i and q data stream. the internal timing of the AD9709 routes the selected i and q data to the correct dac output. in interleaved mode, if no inter- polation tlter precedes the AD9709, the symbol rate will be half that of the system clock driving the digital datastream and the iqwrt and iqclk pins on the AD9709. iouta ioutb qouta qoutb rb ra v mod avdd rl ad8346 ad976x 0 to i outfs v dac dcom fsadji refio sleep r set 3.9k 0.1 f dvdd avdd ca 0.1 f vpbf bbip bbin bbqp bbqn ad8346 loip loin vout iqwrt iqclk acom AD9709 i dac rl la rl cb la rl rb rb rl ra ra avdd rl ca rl la rl cb la rb rb rl ra ra c filter differential rlc filter vdiff = 1.82v p-p q dac latch phase splitter rohde & schwarz fsea30b spectrum anal yzer rohde & schwarz signal generator port i port q tektronics awg2021 w/option 4 d i g i t a l i n t e r f a c e iqsel fsadjq r set 3.9k mode cb = 45pf la = 10 h i outfs = 11ma avdd = 5.0v vcm = 1.2v note: rl = 200 ra = 2500 rb = 500 rp = 200 ca = 280pf q dac i dac latch note: dacs full-scale output current = i outfs ra, rb and rl are thin film resistor networkswith 0.1% matching, 1% accuracy. available from ohmtek ornxxxxd series. ' &( - d* 4 121 >%&, AD9709 #(2# cdma carrier division multiple access, or cdma, is an air transmit/ receive scheme where the signal in the transmit path is modulated with a pseudorandom digital code (sometimes referred to as the spreading code). the effect of this is to spread the transmitted signal across a wide spectrum. similar to a dmt waveform, a cdma waveform containing multiple subscribers can be char- acterized as having a high peak to average ratio (i.e., crest factor), thus demanding highly linear components in the transmit signal path. the bandwidth of the spectrum is detned by the cdma standard being used, and in operation is implemented by using a spreading code with particular characteristics. distortion in the transmit path can lead to power being trans- mitted out of the detned band. the ratio of power transmitted in-band to out-of-band is often referred to as adjacent channel power (acp). this is a regulatory issue due to the possibility of interference with other signals being transmitted by air. regulatory bodies detne a spectral mask outside of the transmit band, and the acp m ust fall under this mask. if distortion in the transmit path causes the acp to be above the spectral mask, then tltering, or different component selection is needed to meet the mask requirements. figure 42 shows the AD9709/ad8346 application circuit of figure 41 reconstructing a wideband, or w-cdma test vector with a bandwith of 8 mhz, centered at 2.4 ghz and being sampled at 62.5 mhz. the if frequency at the dac output is 15.625 mhz. acpr for the given test vector is measured at greater than 54 db. frequency center 2.4ghz 3mhz span 30mhz cu1 c11 e 130 e 120 e 110 e 100 e 90 e 80 e 70 e 60 e 50 e 40 e 30 dbm 1 c2 cu1 c0 c11 ' &$ .*0 >*. 0 ,+ *030 $& 5 / c . 3 e+& - figure 43 shows an example of the AD9709 used in a w-cdma transmitter application using the ad6122 cdma 3 v if sub- system. the ad6122 has functions, such as external gain control and low-distortion characteristics, needed for the superior adjacent channel power (acp) requirements of w-cdma. ( q dac ) iouta qouta qoutb dcom fsadj2 refio sleep r set2 1.9k 0.1 f clk2 q data input i data input dvdd avdd 500 50 500 500 iipp iipn iiqp iiqn ad6122 clk1 fsadj1 r set1 2k r cal 220 500 50 dac latch dac ( i dac ) input latches wrt1 wrt2 acom AD9709 u1 u2 loipp loipn 2 phase splitter refin vgain gain control txopp txopn gain control scale factor temperature compensation modopn modopp v cc v cc 3v 500 500 ioutb input latches 500 50 500 50 dac latch dac 634 ' &% .*) 4121 ,($$ #(># AD9709 evaluation board general description the AD9709-eb is an evaluation board for the AD9709 8-bit dual d/a converter. careful attention to layout and circuit design, combined with a prototyping area, allow the user to easily and effectively evaluate the AD9709 in any application where high resolution, high speed conversion is required. this board allows the user flexibility to operate the AD9709 in vari ous configurations. possible output configurations include transformer coupled, resistor terminated, and single and differ- ential outputs. the digital inputs can be used in dual port or interleaved mode, and are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. when operating the AD9709, best performance is obtained when running the digital supply (dvdd) at 3 v and the analog supply (avdd) at 5 v. wht tp29 wht tp30 wht tp31 wht tp32 dgnd;3,4,5 dgnd;3,4,5 dgnd;3,4,5 dgnd;3,4,5 s1 s2 s3 s4 wrt1in iqwrt clk1in iqclk clk2in reset wrt2in iqsel 1 2 r1 50 1 2 r2 50 1 2 r3 50 1 2 r4 50 1 2 3 jp5 jp16 1 2 3 a b jp4 1 2 3 a b jp3 2 3 5 6 4 1 dgnd;8 dvdd;16 tssop112 1 2 3 a b jp7 jp2 jp1 dvdd 1 2 3 a b jp6 dvdd /2 clock divider wrt1 clk1 clk2 wrt2 wht tp33 sleep 1 2 r13 50 sleep j clk q q pre clr u1 k dvdd 15 ic ic ab ic 1 2 3 a b jp9 dclkin1 dclkin2 14 12 11 9 7 10 13 dgnd;8 dvdd;16 tssop112 j clk q q pre clr u2 k red tp10 b1 ban-jack dvddin l1 bead 1 2 c9 10 f 25v blk tp37 blk tp38 tp43 blk blk tp39 dgnd dvdd b2 ban-jack red tp11 b3 ban-jack avddin l2 bead 1 2 c10 10 f 25v blk tp40 blk tp41 tp44 blk blk tp42 agnd avdd b4 ban-jack 1 2 c7 0.1 f 1 2 c8 0.01 f dvdd power decoupling and input clocks r1 22 inp1 2 1 rcom r2 22 inp2 3 r3 22 inp3 4 r4 22 inp4 5 r5 22 inp5 6 r6 22 inp6 7 r7 22 inp7 8 r8 22 inp8 9 r9 22 10 rp16 r1 22 inp9 2 1 rcom r2 22 inp10 3 r3 22 inp11 4 r4 22 inp12 5 r5 22 inp13 6 r6 22 inp14 7 r7 22 8 r8 22 inck1 9 r9 22 10 rp9 r1 22 inp23 2 1 rcom r2 22 inp24 3 r3 22 inp25 4 r4 22 inp26 5 r5 22 inp27 6 r6 22 inp28 7 r7 22 inp29 8 r8 22 inp30 9 r9 22 10 rp10 r1 22 inp31 2 1 rcom r2 22 inp32 3 r3 22 inp33 4 r4 22 inp34 5 r5 22 inp35 6 r6 22 inp36 7 r7 22 8 r8 22 inck2 9 r9 22 10 rp15 ' && 3 . @ 121 - AD9709 #(1# rp11 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 33 116 rp5, 10 314 rp5, 10 512 rp5, 10 710 rp5, 10 116 rp6, 10 314 rp6, 10 512 rp6, 10 215 13 11 9 15 13 11 dvdd rp3 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 22 rp5, 10 4 rp5, 10 6 rp5, 10 8 rp5, 10 2 rp6, 10 4 rp6, 10 6 rp6, 10 89 rp6, 10 dutp1 dutp2 dutp3 dutp4 dutp5 dutp6 dutp7 dutp8 dutp9 dutp10 dutp11 dutp12 dutp13 dutp14 dclkin1 dvdd rp1 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 22 rp13 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 33 2 p1 p1 1 4 p1 p1 3 6 p1 p1 5 8 p1 p1 7 10 p1 p1 9 12 p1 p1 11 14 p1 p1 13 16 p1 p1 15 18 p1 p1 17 20 p1 p1 19 22 p1 p1 21 24 p1 p1 23 26 p1 p1 25 28 p1 p1 27 30 p1 p1 29 32 p1 p1 31 34 p1 p1 33 36 p1 p1 35 38 p1 p1 37 40 p1 p1 39 116 rp7, 10 314 rp7, 10 512 rp7, 10 710 rp7, 10 116 rp8, 10 314 rp8, 10 512 rp8, 10 215 13 11 9 15 13 11 rp7, 10 4 rp7, 10 6 rp7, 10 8 rp7, 10 2 rp8, 10 4 rp8, 10 6 rp8, 10 89 rp8, 10 dutp23 dutp24 dutp25 dutp26 dutp27 dutp28 dutp29 dutp30 dutp31 dutp32 dutp33 dutp34 dutp35 dutp36 dclkin2 710 rp5, 10 710 rp8, 10 spares 2 p2 p2 1 4 p2 p2 3 6 p2 p2 5 8 p2 p2 7 10 p2 p2 9 12 p2 p2 11 14 p2 p2 13 16 p2 p2 15 18 p2 p2 17 20 p2 p2 19 22 p2 p2 21 24 p2 p2 23 26 p2 p2 25 28 p2 p2 27 30 p2 p2 29 32 p2 p2 31 34 p2 p2 33 36 p2 p2 35 38 p2 p2 37 40 p2 p2 39 rp12 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 33 dvdd rp4 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 22 dvdd rp2 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 22 rp14 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 33 inp1 inp2 inp3 inp4 inp5 inp6 inp7 inp8 inp9 inp10 inp11 inp12 inp13 inp14 inck1 inck2 inp23 inp24 inp25 inp26 inp27 inp28 inp29 inp30 inp31 inp32 inp33 inp34 inp35 inp36 digital input signal conditioning ' &+ 0 . AD9709 #$# wht tp46 12 r10 1.92k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 db13p1msb db12p1 db11p1 db10p1 db9p1 db8p1 db7p1 db6p1 db5p1 db4p1 db3p1 db2p1 db1p1 db0p1 dcom1 dvdd1 wrt1 clk1 clk2 wrt2 dcom2 dvdd2 db13p2msb db12p2 mode avdd ia1 ib1 fsadj1 refio gainctrl fsadj2 ia2 ib2 acom sleep db0p2 db1p2 db2p2 db3p2 db4p2 db5p2 db6p2 db7p2 db8p2 db9p2 db10p2 db11p2 u2 1 2 c1 val 1 2 c2 0.01 f 1 2 c3 0.1 f dvdd 1 2 3 a b jp8 dvdd 1 2 c11 1 f 1 2 c12 0.01 f 1 2 c13 0.1 f avdd sleep dutp36 dutp35 dutp34 dutp33 dutp32 dutp31 dutp30 dutp29 dutp28 dutp27 dutp26 dutp25 1 2 c15 10pf 1 2 r7 50 1 2 c6 10pf 1 2 r8 50 wrt1 clk1 clk2 wrt2 dutp23 dutp24 dutp1 dutp2 dutp3 dutp4 dutp5 dutp6 dutp7 dutp8 dutp9 dutp10 dutp11 dutp12 dutp13 dutp14 1 2 c4 10pf 1 2 r5 50 1 2 c5 10pf 1 2 r6 50 tp34 wht r11 val 1:1 3 2 16 4 nc = 5 t1 agnd;3,4,5 s6 out1 tp45 wht 12 r9 1.92k tp36 wht refio 1 2 c14 0.1 f dut and analog output signal conditioning 1 2 3 a b jp15 avdd mode acom bl1 bl2 1 2 c16 22nf 12 r15 256 1 2 c17 22nf 12 r14 256 jp10 tp35 wht r12 val 1:1 3 2 16 4 nc = 5 t2 agnd;3,4,5 s11 out2 bl3 bl4 ' &, 121 8 0 . AD9709 #$(# ' &2 ) 0 AD9709 #$$# ' &> - 0 AD9709 #$%# ' &1 6 ( ) 0 AD9709 #$&# ' + 6 $ 5 3 AD9709 #$+# ' +( 6 % 3 3 AD9709 #$,# ' +$ 6 & - 0 AD9709 #$2# 48-lead thin plastic quad flatpack (lqfp) (st-48) top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 0 min coplanarity 0.003 (0.08) seating plane 0.006 (0.15) 0.002 ( 0.05 ) 7 0 0.057 (1.45) 0.053 (1.35) outline dimensions dimensions shown in inches and (mm). .%2(#>#+=f g,, 3!)!40 |
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